fmmarques.make.v101 - Make system, Rule syntax, variables

Abstract This is the first installment of the make tutorial. The make tutorial is devised to help you learn about make, and to apply that knowledge to the automatization of the compilation process. In this installment we will focus on the make system, rule syntax, and defining and using variables.

I. Make system, rule syntax, variables

A. Make system

Make is a tool that allows the programmer to write rules, in order to accomplish tasks. As such, make can be used to automatize many tasks, but its main use is in programming projects that are deployed in source format.

Many open source projects take advantage of make, since it’s readily available on all GNU/Linux systems. Calling ”make”, will cause the make system to search for a Makefile file, in the directory. The first rule encountered will be handled as the default target. Make will try its best to accomplish every dependency of the target, and the target itself.

A Make rule target has a special characteristic: it represents a file. When a rule is applied, and a target is fulfilled then a file is traditionally created.

B. Rule syntax

A rule has a specific format, comprised of three elements: target, dependencies and commands. Lets see a example,
Listing 1.  Makefile

all: one
  echo ”I’m_executing_’all’_target.”

The result of the ”make” command will fail. When you run the command, make will try to create ”all” file. Its first action will be to check the ”one” dependency, and this is where our Makefile fails. ”one” file does not exist, do ”all” cannot be executed, and make complains it does not know how to create ”one”.

Lets make an addedum to the Makefile.
Listing 2.  Makefile

all: one
  echo ”I’m_executing_’all’_target.”

one:;

With the inclusion of the new rule, make now knows how to accomplish ”one”. If you execute ”make”, you’ll be greeted with

echo ”I’m_executing_’all’_target.”
I’m executing ’all’ target.

Note: You can silence an echo command with a @ before the command (i.e. @echo).

There is a interesting point to the file-as-target system followed by make. If you do not create a file, and both the ”all” and ”one” rules don’t, the rule will always execute.

Try the following

touch one all

If you try to execute make, you’ll be informed that all ’all’ is up to date. However if you do,

rm one all
touch all one

And try make again, now you’ll be again greeted by the ”I’m executing ’all’ target.” again. This is because the ’all’ file is just a little bit older than ’one’, and since make should update ’all’ when ’one’ is younger, ’make’ always tries to execute every command associated with the ’all’ target.

C. Variables

Variables are useful in Makefiles. By default every variable is a space separated list of textual elements. This means that when you set a variable to ”abc def” the variable has two elements: ”abc” and ”def”. There is a syntax for assigning value to variables, and for referencing the value within the variable. When used directly, the programmer is assigning a value to the variable, or defining it. When used with $(¡name¿) the programmer is using its variable.

There are also two flavors of variables in Makefile. The recursively expanded variable, which are defined with ’=’, and its evaluation is based on recursive expansion.
Listing 3.  Makefile

rof=$(t)
t=$(lol)
lol=Not laughing
all:; echo $(rof) # $(rof) is ”Not laughing”.

This flavor has two disavantages. One: it does not handle appending. Something like,
Listing 4.  Makefile

lol=$(lol) $(lol) # Infinite loop detected

Will cause infinite expansion. The second disavantage is with functions will be rerun every time the variable is evaluated. There are functions that will be studied in the next installments, like the wildcard that may cause unexpected results when ran.

Variables may be used both as targets or as dependencies. Example follows
Listing 5.  Makefile

DEPENDENCIES=main.c module.c
OBJECTS=main.o module.o
OUTPUT=main

$(OUTPUT): $(OBJECTS)
  echo ”I’m_executing_’all’_target.”

$(OUTPUT) is substitute for main. $(OBJECTS) is substituted for the ”main.o module.o”.

II. See also

A. Related posts

fmmarques.make.v102 - Implicit rules, extensions and wildcards.

B. Bibliography

Rule Syntax - GNU make: Rule syntax

Basics of Variable References - GNU make: Refence

fmmarques.make.v102 - Implicit rules, extensions and wildcards.

Abstract In this installment, we will dwell into make and more advanced features. In the first installment, a simple overview was provided giving focus on rule formation, with target and dependencies thoroughly explained. Now, I’ll explain how to form more sofisticated rules, based on wider (or stricter) matching patterns.

I. Implicit rules, extensions and wildcards

A. Implicit rules

Implicit rules are rules well known by make. When make was written, C programming language was on its prime and the compilation process was well defined. GNU therefore decided to implicitly include that knowledge in make. When a rule states that a dependncy is a file with .o extension, this will cause the compilation of the same file with c extension. Listing 1.  hello.c

#include <stdio.h>

int main( int argc, char *argv[]) {
  printf(”Hello_world.”);
  return 0;
}

The above can be compiled with the following Makefile. Listing 2.  Makefile

hello: hello.o
    $(CC) -o hello hello.o

At this point, we have two files: hello.c and Makefile on the same directory. The execution of the command ”make” in the directory where hello.c (and Makefile) resides gives rise to the creation of hello.

How does this work? Make knows that in order to create the binary file hello, it must have a hello.o file available. We only created hello.c, and it is not even referenced in the Makefile, so what gives?

Make does know that when one compiles and does not link a source file, the file created is given the same basename with .o extension. With that knowledge, make extrapolates that since hello depends on hello.o, and since %.o files are compilations of respective %.c files (i.e. ”gcc -c hello.c” creates hello.o) there must be a hello.c file in the directory. If there is, timestamps are compared and if hello.c is newer than hello.o or hello.o does not exist, then the command ”$(CC) -c hello.c” command insues.

Note: $(CC) is a make variable standing for C compiler. You can do CC=gcc in the beginning of the Makefile.

B. Extensions

GNU make provides several builtin extensions, like basename or addprefix. These can ben proven useful in some situations. Continuing with our example, lets add two other C source files, Listing 3.  main.c

#include <stdio.h>

int hello();
int world();

int main(int argc, char *argv[]) {
  hello();
  world();
  return 0;
}

Listing 4.  world.c

#include <stdio.h>

int world() {
  printf(”world.”);
  return 0;
}

Lets also modify the hello.c file to contain the following code, Listing 5.  hello.c

#include <stdio.h>

int hello() {
  printf(”Hello”);
  return 0;
}

We have now three different C source files: hello.c, world.c and main.c. main.c contains the main function, and it is considered the main module. It also declares the signatures of both hello and world functions, which are defined within their respective modules.

Note: A function declaration is the simple statement of the function’s signature while a function definition contains the body of the function.

Now we must also update Makefile content to make sure the compilation process will include the new files, Listing 6.  Makefile

main: hello.o world.o main.o
    $(CC) -o main main.o hello.o main.o

Now ”make” will create ”main” which, when executed, will print out ”Hello world”.

Let us simplify the Makefile with extensions, if we can. Listing 7.  Makefile

DEP=hello world main
main: $(addsuffix .o,$(DEP))
    $(CC) -o $@ $<

Note: addsuffix applies the first operand as a suffix to every element of the second operand.

Now, every time main is targeted, the list of names in DEP gets appended with a .o causing make to regenerate .o files as needed. This depends on the implicit rule that generates .o from .c files. The rule now can also be revamped to use the target and first dependency operators, $@ and $¡ respectively. See the first installment for more informations on these operators, rule syntax and variables.

As anyone who’ve ever delt with a large enough project can tell, this rules help with maintining the Makefile and the project itself; you online add (or remove terms) from the first line and the compilation process adapts to the newly added (or removed) items.

C. Wildcards

Wildcards are syntatic sugar to help the Makefile programmer to write smaller, more concise rules. Lets explore the running example, Listing 8.  Makefile

DEP=$(wildcard *.c)
main: $(patsubst \%.c,\%.o,$(DEP))
    $(CC) -o $@ $<

Note: wildcard expands the pattern given to a list of existing filenames that correspond to the pattern.

Note: patsubst substitutes the explicit part of the name for another. % stands for whatever is not matched.

In this form, we automatically add all the C source files to the compilation process and create the main from these.

There is yet another flavor for wildcards in make, that are used for pattern matching. These will be covered on the next installment.

II. See also

A. Related posts

fmmarques.make.v101 - Make system, Rule syntax, variables

B. Bibliography

Functions for String Substitution and Analysis - GNU make: Text functions

Function wildcard - GNU make: Wildcard Function